1. Field of the Invention
The present invention relates to semiconductor devices and their manufacture, and more specifically to a structure and method of making a field effect transistor (FET) having an embedded stressor.
2. Description of the Related Art
The industry trend in semiconductor technology is to create smaller devices that are faster than their predecessors. Reduced power consumption on chips is another crucial issue that drives innovation in this area. In this regard, complementary-metal-oxide-semiconductor (CMOS) circuits have become prevalent because of reduced power requirement and size. CMOS circuits often use a combination of p-type and n-type metal-oxide-semiconductor field effect transistors (MOSFETS) to implement logic gates and other circuit functions. It has been found that improved performance and reduced power requirement can be obtained when a stress is applied to the channel region of a MOSFET transistor to create a strain therein. A combination of silicon and silicon-germanium alloys have been used to induce a beneficial strain in transistors of CMOS circuits. Recently, an improved process referred to as embedded silicon germanium technique has been implemented with benefits to performance and reduced power.
The embedded silicon germanium technique involves forming trenches adjacent to extension regions 126 of a transistor and growing an epitaxial layer of silicon germanium therein. In an example of a prior art FET 190 depicted in FIG. 1, embedded silicon germanium stressor regions 135 can have substantially straight walls 122 adjacent to extension regions 126. The extension regions can be adjacent to a channel region 120 under a gate 128 of the transistor. The walls 122 extend in a vertical direction 124 (i.e., at a direction normal to a major surface 104 of the active semiconductor region) to a bottom surface 141, the bottom surface being at a depth below the major surface 104. The stressor regions 135 may be “overfilled” in that they can extend to a height 155 above the major surface 104.
The prior art PFET design as shown in FIG. 1 can pose practical design challenges. When the vertically extending walls 122 of the stressor regions are close to the channel region 120, outdiffusion of a dopant (typically boron for a PFET) from the stressor regions 135 can degrade short channel effects. If a SiGe buffer layer having a germanium concentration below the germanium concentration of the stressor regions 135 is disposed between the extension regions and the stressor regions, it can be difficult to perform a correct linkup implant to electrically connect the extension region, the buffer layer and the stressor region.
The vertical walls 122 can also allow crystal defects to occur in unwanted locations which are apart from the planes in which the vertical walls are disposed. Further improvements in the structure and fabrication of embedded silicon germanium FETs are desirable.